1. Field of the Invention
The present invention relates to a memory test circuit enabling a central processing unit (CPU) to test a memory having a data width greater than the data width of the data bus linking the memory to the CPU.
2. Description of the Related Art
So-called system-on-a-chip devices, for example, are often structured to transfer data directly between memory and peripheral computational circuits on a wide data bus, without the intervention of the CPU. One example of such a device is described in Japanese Patent Application Publication No. 2000-357372. When the device is fabricated, it is tested by having the CPU execute a self-test program. As part of the self-test, the CPU must write test patterns in the memory, so a memory test circuit, which is a type of switching circuit that connects the memory to the CPU, is provided. If the width of the CPU data bus is less than the data width of the memory, the memory test circuit must also convert the data width.
FIG. 1 schematically shows a conventional memory test circuit. This memory test circuit tests a memory (MEM) 1 having an m-bit data width by using a CPU 2 having an n-bit data bus (m>n). To convert between m-bit and n-bit data, the circuit includes an m-bit register (REG) 3, L n-bit registers 41, 42, . . . , 4L (where L is the least integer equal to or greater than m/n), and a selector (SEL) 5. Register 3 is coupled between the data input-output terminals of the memory 1 and registers 41-4L. Registers 41-4L are coupled in parallel to the data bus of the CPU 2. Selector 5 selects n-bit portions of the data stored in register 3 and supplies the selected data to the CPU 2.
In this type of memory test circuit, an m-bit word of data written into the memory 1 is first written from the CPU 2 into registers 41-4L as separate n-bit portions of write data WDT, requiring L write cycles; then the n-bit portions of write data are transferred all at once through register 3 into the memory 1. Similarly, m-bit data read from one word in the memory 1 are stored in register 3 temporarily, and the stored data are divided into n-bit portions in selector 5 and sequentially supplied to the CPU 2 as read data RDT. Accordingly, even though the memory 1 can input or output m bits per cycle, each reading or writing operation requires (L+1) cycles.
In, for example, a memory test using the marching cubes algorithm (a specific procedure for which will be given later), a total of ten test cycles, including six write cycles and four read cycles, are inherently necessary for each word in the memory 1. In the memory test circuit described above, (L+1) times as many cycles are required; that is, 10(L+1) cycles are required. Even in a simpler memory test using a checker pattern or the like, that inherently requires only four cycles (two write cycles and two read cycles) per word, 4(L+1) cycles are needed, and in a memory test using a diagonal pattern, 2(L+1) cycles are required for writing and reading.
The conventional memory test circuit described above is problematic because the test data must be written from the CPU 2 into registers 41-4L in multiple separate portions, greatly increasing the necessary number of test cycles.